1. Field of the Invention
The present invention relates to a display device and a driving method thereof.
2. Discussion of the Related Art
Display devices, which are delivery media of visual information, have been applied to various information devices or office machines. A cathode ray tube or a Braun tube, which is a widely available display device, has a problem that its weight and volume are great. Many kinds of flat panel displays capable of overcoming this limitation of the cathode ray tube have been developed, including a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode device (OLED), and the like.
In flat panel displays, data lines and scan lines are arranged orthogonally to each other, and pixels are arranged in a matrix form. In the LCD or OLED, the scan lines are also referred to as gate lines since gate electrodes of TFTs are connected to the scan lines. Video data voltages to be displayed are supplied to the data lines, and scan pulses (or gate pulses) are sequentially supplied to the scan lines. The video data voltages are supplied to pixels of the display lines to which the scan pulses are supplied. While all the display lines are sequentially scanned by scan pulses, video data are displayed.
Generally, a scan driving circuit for supplying the scan pulses to the scan lines of the flat panel display includes a plurality of scan integrated circuits (hereinafter, referred to as “ICs”). Since each of the scan ICs needs to sequentially output scan pulses, it includes a shift register. It may also include circuits and output buffers for controlling an output voltage of the shift register according to driving characteristics of a display panel. This scan driving circuit operates in response to control signals generated from a timing controller. Hereinafter, a scan driving circuit of a flat panel display will be described based on a scan driving circuit of an LCD.
FIG. 1 shows a related art gate IC of a scan driving circuit applied to an LCD. As shown in FIG. 1, the gate IC includes a shift register 10, a level shifter 12, and a plurality of logic AND gates 11 (hereinafter, referred to as “AND gates”) connected between the shift register 10 and the level shifter 12.
The shift register 10 sequentially shifts gate start pulses GSP according to the gate shift clock GSC by using a plurality of dependently connected flip-flops. Each of the AND gates 11 performs an AND operation on the output signal of the respective flip-flop of the shift register 10 and an inverted gate output enable signal GOE to generate an output. The gate output enable signal GOE is inverted by an inverter 13, and input to one input terminal of the AND gates 11. The level shifter 12 shifts the swing width of the output voltage of the AND gate 11 to an extent at which a TFT of the LCD can operate. Output signals G1 to Gk of the shift register 12 are sequentially supplied to k (k is an integer) gate lines.
FIG. 2 shows related art examples of control signals for controlling a scan driving circuit and an output signal of the scan driving circuit. As shown in FIG. 2, a related art gate IC receives a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE to output gate pulses G1 and G2 of one horizontal period (H), i.e., one cycle of the gate shift clock GSC.
The gate pulses G1 and G2 are for operating TFTs of a flat panel, in this example an LCD panel. In order to supply a voltage that can turn on the TFTs of the LCD panel, the width of a high logic period in the gate pulses G1 and G2 needs to be sufficiently long. In the related art device, as shown in FIG. 2, the TFTs can be operated even when the width of the gate pulses G1 and G2 is one horizontal period (H) as a horizontal period (H) tended to be relatively long. However, as the panels become larger and the resolution higher, one horizontal period (H) tends to become shorter. Therefore, when the width of the gate pulses G1 and G2 is set to one horizontal period (H), the TFTs may not be turned on or turned off at a desired timing.
In an effort to solve the above problem, a ‘gate overlap’ has been proposed in which the width of the high logic period of the gate start pulse GSP is increased to two horizontal periods (H) as show in FIG. 3.
However, when the gate start pulse GSP is input for two horizontal periods (H) as shown in FIG. 3, a ‘gate off’ phenomenon may occur in which the voltage level of the gate pulses G1 and G2 falls during the high logic period of the gate output enable signal GOE, thereby potentially causing a temporary cut-off period while source output data are to be transferred to pixels of the panel.
Moreover, when the high logic period of the gate pulses G1 and G2 is maintained for two horizontal periods (H) without the ‘gate-off’ phenomenon, the voltage charged in the pixels of the LCD panel is influenced by the data voltage of the previous frame during one horizontal period (H) while the gate pulses G1 and G2 overlap each other. Therefore, when the difference in data from the previous frame to the current frame is large, the charge rate of a source output waveform may fall.